Conventional semiconductor integrated circuit devices of the type described above include the one shown in FIG. 2.
The area on a chip 1a of a semiconductor integrated circuit device 1 is divided roughly into a core area 2 and an I/O area 3. On the core area 2, testee circuits 4 and test control circuits 5 are provided.
In the I/O area 3, I/O cells 6 and tester circuits 7 are provided. The I/O cells 6, being connected to a pad 8 which is an I/O terminal for connection to the outside, include a buffer amplifier for storing and amplifying a signal when outputting a signal from the testee circuit 4 in the core area 2 to the outside and when inputting a signal from outside. An electrostatic destruction protection circuit called ESD is also provided for preventing the destruction of an internal circuit due to electrostatic from outside. C.sub.in is an external control signal provided from the outside and C.sub.dc is a test control signal as decoded by the test control circuits 5.
In this configuration, when conducting a test on functions of a semiconductor integrated circuit 1, the external control signal C.sub.in is given from outside and the test control signal C.sub.dc as decoded by the test control circuits 5, is output to the testee circuit 4 and the tester circuits 7 in the I/O area 3; various types of test including the above-described internal scan method, the boundary scan method and the internal memory direct access method are then conducted.
However, such a conventional semiconductor integrated circuit device 1 has a disadvantage: that the placing of the test control circuits 5 in the core area 2 necessitates securing an area in the core area 2 for placing the test control circuits 5 thereon, thus resulting in a larger chip size of a semiconductor integrated circuit device 1.
The conventional technology used also has a disadvantage in that it causes the laying out to become complex because a layout designer must take into account the disposition of the test control circuits 5. Particularly, when a user designs the core area 2, the presence of the test control circuits 5 in the core area 2 presents a problem. Normally, a user does not need the test control circuits 5. In many cases, it is a manufacturer of the semiconductor integrated circuit device 1 who uses the test control circuits 5. Forcing the user to design the core area 2 in consideration of the unnecessary test control circuits 5 is undesirable.
Moreover, the conventional device has a disadvantage in that it has a complicated wiring structure because the external control signal C.sub.in must be delivered to the core area 2 via a test control signal line distributed to the tester circuits 7 in the I/O area 3, resulting in complex wiring.